This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder.
When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel).
To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds.
This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder.
The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio.
The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform.
This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.
The IP offers two encoder variants to meet the different targets of features.
The IP include 2 mode.
H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)
The IP core is smaller but yields less compression. It does not require external memory.
H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:
The IP core is larger but offers a significantly better compression.
Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.
The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.
The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
Single Chip Solution
32-bit RISC MCU
Video Process Engine
Video DAC/Audio DAC
Easy Integrated Customer’s Logic
DVR and POS DVR
ATM machine surveillance
Home stay monitoring
Multiple channel IP camera
This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design. The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals. The module allows easy connectivity to an external ADC with up to 16-bit signed input samples.
Short range telemetry
This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates.
High-speed filter applications where resources are limited
General purpose FIR filters with symmetrical coefficients
This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering.
Values are sampled on the rising clock-edge of clk when EN is high. The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles.
IIR filtering in higher sample-rate applications
General purpose high-pass, band-pass and low-pass filters
This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB.
Digital video and image processing
DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing.
Pixels are extracted from the BT.656 input stream and converted to RGB888 format.
BT.656 input video capture and processing
PAL & NTSC SDTV interlaced format conversion