Power Quencher® Capless LDO (Silicon-proven 40 nm, 3 mA, excellent quiescent current for IoT)
This series of low-power, fully-integrated low dropout (LDO) voltage regulators achieves a low-noise output voltage without external components, thus saving package pins and valuable PC board space. These LDOs are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.
The MIPG PHY is part of the A family of devices - which includes the MIPG PHY-031, MIPG PHY-033, and the MIPG PHY. It is A company’ 4th generation, single port 10/100/1000 Mbps Tri-speed Ethernet PHY. It supports RGMII interface to the MAC.™
The MIPG PHY provides a low power, low BOM (Bill of Materials) cost solution for comprehensive applications including consumer, enterprise, carrier and home networks such as PC, HDTV, Gaming machines, Blue-ray players, IPTV STB, Mdia Players, IP Cameras, NAS, Printers, Digital Photo Frames, MoCA/Homeplug (Powerline)/EoC/ adapters and Home Router & Gateways, etc.
Ultra-High Accuracy Bandgap Reference in 130 nm (VBRS1000NT130)
ACCUREF™ Bandgap Reference (Silicon-proven 40 nm, low-power, low-noise, ultra-precise single-digit mV accuracy, no external components required)
ACCUREF™ Voltage and Current References: This series of low-power, low-noise IP cores generates a precise, adjustable reference voltage with single-digit millivolt (mV) accuracy over a wide temperature range without external components. With their unique design that improves upon current products by allowing the systems to operate with ultra-low levels of power consumption without sacrificing accuracy or noise performance, our family of ACCUREF™ voltage and current reference IP cores support a broad range of industry applications with improved efficiency and remarkable area savings overall.
Ultra-low Power Voltage Reference in 40 nm (VVR060LT040)
Voltage Reference for Integrated PMU (Silicon-proven 40 nm, low-power for IoT with quiescent current of <0.9 μA)
This series of fully-integrated low power voltage references generates a 0.6 V output voltage and supports an input from 2.8 to 4.2 V. They operate at an ultra-low quiescent current of < 0.9 μA. These voltage references are silicon-proven in a 40 nm process and are a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications.
8/12-bit JPEG decoder for ASIC and FPGA with scalable
This JPEG decompression IP core supports the Baseline Sequential DCT and Extend- ed Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extreme- ly high pixel rates.
The JPEG-ST-V Decoder decompresses JPEG images and the video payload for Mo- tion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-MT-V Encoder Core. This Encoder-Decoder pair pro- vide an extremely cost effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.
Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro- cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
This JPEG compression IP core supports the Baseline Sequential DCT and the Ex- tended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less pow- er than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200.
The JPEG-MT-V Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame vid- eo.
Once programmed, the easy-to-use encoder requires no assistance from a host pro- cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed da- ta, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Stream- ing interface.
The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃.
The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary.
The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary.