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| 140 mA Buck DC-DC Converter in 40 nm (VBKS0140T040) | 参考报价 | 无资料 | 无资料 | 40 nm |  |
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| Buck DC-DC Converter for Integrated PMU (Silicon-proven 40 nm, 140 mA, optimized clocking to eliminate spurious emissions for low system noise) This series of buck DC-DC converters delivers up to 140 mA of load current and features optimized clocking options to eliminate spurious emissions resulting in much lower system noise. This buck DC-DC converter is silicon-proven in a 40 nm process and is a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications. | 概述 | |||||
| 400 mA Buck DC-DC Converter in 110 nm (VBKS0400T110) | 参考报价 | 无资料 | 无资料 | 110 nm | |
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| Buck DC-DC Converter (Silicon-proven 110 nm, 400mA, excellent efficiency) The VBKS0400T110 IP core is a Buck DC-DC switching converter that delivers up to 400 mA of load current. It includes voltage, current and clock references, power-on-reset circuitry, overcurrent protection, a temperature sensor and ESD protection. Soft-start circuitry prevents high currents during start-up, and soft-stop circuitry provides a controlled shut-down sequence during a sudden shut down or fault detection. | 概述 | |||||
| 300 mA Capless LDO in 130 nm (VLDS0300LS130) | 参考报价 | 无资料 | 无资料 | 130 nm | |
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| Power Quencher® Capless LDO (Silicon-proven 130 nm, 300 mA, excellent quiescent current and load transient regulation) The Power Quencher® series of fully-integrated low dropout (LDO) voltage regulators operates with ultra-low levels of power consumption without sacrificing other areas of performance. They achieve a low-noise output voltage and do not require the external output capacitor that is typically needed in an LDO for loop stability and noise reduction. This saves component count, board space and cost, and improves overall system reliability. The Power Quencher® LDO voltage regulator IP cores are optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and Internet of Things (IoT) applications. | 概述 | |||||
| 300 mA Capless LDO in 180 nm (VLDS0300RNM180) | 参考报价 | 无资料 | 无资料 | 180 nm | |
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| Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling) Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications. | 概述 | |||||
| MIPI M-PHY Gear 4 IP in TSMC 12nm FFC | 参考报价 | 无资料 | 11 GHz | 12 nm | |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | 概述 | |||||
| DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ | 参考报价 | 无资料 | 25 MHz | 28 nm | |
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| A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard | 概述 | |||||
| PCI Express Gen4 PHY IP in 28nm HPC+ | 参考报价 | 无资料 | 25 MHz | 28 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | 概述 | |||||
| PCI Express Gen4 PHY IP in TSMC 12nm FFC | 参考报价 | 无资料 | 25 MHz | 12 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | 概述 | |||||
| Rapid IO PHY in 65nm | 参考报价 | 2.295 μm^2 | 25 Hz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | 概述 | |||||
| Low power oscillator | 12000 点 | 100.100 μm^2 | 32 KHz | 40 nm | |
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| OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range. | 概述 | |||||
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