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| 4.2V-to-1.2V DC/DC Converter | 参考报价 | 40.000 K μm^2 | 1 MHz | 130 nm |  |
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| The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. | 概述 | |||||
| 4.2V-to-1.8V DC/DC Converte | 参考报价 | 40.000 K μm^2 | 1 Hz | 130 nm | |
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| The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary. | 概述 | |||||
| PLL with Multiple Output Frequency | 参考报价 | 40.000 K μm^2 | 12.156 MHz | 130 nm | |
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| The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 点 | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_564144 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | 概述 | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 点 | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_809744 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | 概述 | |||||
| 14 Bit Rail to Rail DAC | 60000 点 | 75.000 K μm^2 | 1 MHz | 110 nm | |
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| UIP_DAC14_1M_392231 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. This DAC IP is self-biased and optimized for low power and small area. At 1 MHz conversation rate, it only consumes 680uA to drive 15K/50pF loading and occupies silicon area of 0.075 mm2. APPLICATIONS General purpose digital to analog converter Battery monitory system Housekeeping Auxiliary functionality | 概述 | |||||
| 14-Bit 1MSPS DAC in GSMC110nm | 参考报价 | 75.000 K μm^2 | 1 MHz | 110 nm | |
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| MIC_DAC14 is compact and low power 14-bit digital-to-analog converter silicon IP. It features wide range input supply voltage from 1.7V to 5.6V. Its single-end output ranges from 0.1 to 0.9 of supply voltage. | 概述 | |||||
| 10-bit 300 MSPS Video DAC IP in 90 nm | 60000 点 | 76.000 K μm^2 | 300 MHz | 90 nm | |
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| The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format. A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes. APPLICATIONS Composite Video (CVBS) HDTV RGB Video DAC Output Model | 概述 | |||||
| PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 92.400 K μm^2 | 27 MHz | 28 nm | |
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| It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. | 概述 | |||||
| PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process | 参考报价 | 109.850 K μm^2 | 50 MHz | 28 nm | |
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| It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz. The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise. | 概述 | |||||
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